1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor device and, more particularly to, a semiconductor manufacturing method advantageously applied to highly integrated semiconductor device.
2. Description of the Related Art
As the complexity of integration for semiconductor devices has increased, devices and processes for their fabrication have been changed accordingly. For example, changes are required for fabrication of well and isolation features.
First, a well is required to maintain shallow depth. In a conventional method, the well has deep depth of several xcexcm. However, as the depth of source/drain regions has become remarkably shallow, the well also has become shallow for stabilized driving of transistor. Future well depths are expected to be shallower. For example, a transistor can be driven stably with a well having a depth of several thousands A by development of a doping method. Therefore, minimum well depths will be reduced continuously.
Second, a new method for isolation is required. As is well known, LOCOS process has been widely used for isolation; however, it has a limitation in realizing highly integrated devices. Therefore, a STI (Shallow Trench Isolation) process has been proposed as a substitute for the LOCOS process. However, in a device of less than sub-0.1 xcexcm, problems arise because voids are generated during the gap-fill process.
Third, effective control of the amount of dopants on the interface of active region and field region is required. However, in a conventional STI process, it is impossible to isolate according to the doping type of the active region. Therefore, it is also impossible to dope in a well because of well dopant damage due to dopant shift from the active region to the field region around the active region, respectively by in the N-well and P-well. Recently, a method has been found to control the amount of P-well dopant. However, problems of N-well counter doping and N-well dopants are still unsolved. As the degree of integration has increased, inverse narrow width effects are accordingly increased. Therefore, solutions are required to solve these problems.
However, the above-mentioned integration in well and isolation features has several drawbacks.
First, a well becomes shallow as a result of development of the doping method. However, the well is formed by ion-implantation, therefore, it is impossible to avoid crystal defects due to ion implantation. Moreover, there is a problem that the profile of the dopant is not uniform, but has a slope.
Second, the STI process is advantageous to high integration, compared with the LOCOS process. However, this STI process has a limitation in devices of sub-0.1 xcexcdepths. In short, the STI process has problems of gap-fill such as void generation in filled oxide due to an increase in the trench aspect ratio and in the generation of transformation or defects in the active surface in a succeeding process due to increase surface stress in the parts thereof. Additionally, problems of lowering of transistor properties result from a decrease of carrier mobility due to stress and deterioration of transistor driving by unevenness in the oxide thickness and due to interface trap between the oxide and the substrate.
In order to solve the problems of gap-fill, research in progress has been directed to development of new materials and processes. A method for reducing the aspect ratio of a trench has been proposed in order to solve the problems; however, the proposed solutions may also result in lowering the degree of integration.
Stress during the gap-fill process is concentrated around the active region on the surface or at the bottom of the trench. It has little effect on a device having a critical size larger than sub-0.1 xcexcm, for example, sub-0.15 xcexcm since the active region has sufficient width. However, in the device of sub-0.1 xcexcm, stress has a greater effect, thereby reducing carrier mobility and generating defects. As a result, electric properties are lowered, and thereby causing difficulties in selection of succeeding processes.
As the degree of integration is increased, side treatment to the interface of active region and to the field region becomes more important. It is more important in isolation by STI. For effective sidewall treatment, it is desirable that the N-well side and the P-well side be treated, respectively. However, according to the present STI, it is difficult to treat the sides respectively. As a result, effective sidewall treatment to the interface between the active region and the field region is not accomplished by the present methods and there is no effective interface treatment method for sub-0.1 xcexcm.
Therefore, an object of the present invention is to provide a method for fabricating semiconductor devices capable of maintaining uniformity of well dopant profile while preventing crystal defects due to doping.
Another object of the present invention is to provide a method for fabricating semiconductor devices that are capable to solve the problems of gap-fill and stress in the STI process.
Still another object of the present invention is to provide a method for fabricating a semiconductor device capable of accomplishing N-well side treatment and P-well side treatment, respectively.
Moreover, still another object of the present invention is to provide a method for fabricating a semiconductor device capable of being applied to highly integrated devices by forming a shallow well and isolation layer by a masking process.
In order to accomplish the above objects, there is disclosed herein a method for fabricating semiconductor device comprising the steps of providing a first conductive silicon substrate having an active region and field regions thereon and having a formed pad oxide layer on the surface, forming a trench having a width including the active region and field regions at both sides of the active region by etching the pad oxide layer and the silicon substrate, forming a spacer having a width similar to that of the field region at both sidewalls of the trench and exposing the active region of the silicon substrate, forming a second conductive well on the exposed active region of the silicon substrate by growing an in-situ doped silicon epi layer to a height similar to a surface of the silicon substrate, depositing an oxide layer on the resultant structure to fill a gap between the spacer and the well, and performing planarization of the oxide layer to expose a surface of the silicon substrate and to form isolation layers at both sides of the well. In another embodiment, there is disclosed a method of fabrication a semiconductor device according to the present invention comprises the steps of: providing a first conductive silicon substrate having a pad oxide layer on a side thereof; forming a trench having a width including the active region and field regions at both sides thereof by etching the pad oxide layer and the silicon substrate, forming a first sidewall layer on an inner side of the trench and on the pad oxide layer using an oxidation process, depositing a first oxide layer on the first sidewall to have a thickness similar to the width of the field region; forming a spacer exposing active region of the silicon substrate on both sides of the trench by etching the first oxide layer, forming a second conductive well comprising the doped silicon epi layer and having a facet by growing in-situ a doped silicon epi layer on the exposed active region of the silicon substrate to a height similar to the surface of the silicon substrate; forming a second sidewall on the surface of the well by using an oxidation process, depositing a second oxide layer having a predetermined thickness on the resultant structure to fill a gap between the spacer and the facet of the well, performing a first planarization of the second oxide layer to expose the first sidewall layer, and performing a second planarization of the resultant structure to expose the surface of the well and to form an isolation layer. According to the present invention, the spacer has a width of 80xcx9c100% relative to that of the field region. According to the present invention, the silicon epi layer is rapidly grown at a high temperature of 900 to 1050xc2x0 C. in the profile region perpendicular to the spacer and the silicon epi layer is slowly grown at a low temperature of 700 to 850xc2x0 C. in a facet formation region; therefore, the upper facet formation layer of the silicon epi layer is thinner than the lower part thereof.
Further according to the present invention, the second oxide layer has a thickness of from 0.2 to 0.9 xcexcm.
Moreover, according to the present invention, the first planarization is performed by Chemical Mechanical Polishing so that the second oxide layer remains to a thickness of 0.05 to 0.12 xcexcm from well surface. The second planarization is performed by Wet Dip.
The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.